1. Field of Invention
This invention is in the field of defect localization analysis of semiconductor devices and calibration apparatus and method for such defect localization.
2. Related Art
During design and verification stage of semiconductor devices, it is important to test for various defects or problematic areas of the chip design that may lead to defects. One class of defects are those causing localized heating of the chip. During the testing stage, it is important to identify such defects. One method for identifying localized heating defects is called Lock In Thermography (LIT). A current product available from the subject assignee, DCG Systems, Inc., of Fremont, Calif., uses this technique and is called ELITE™. The term LIT refers to a non destructive technique that detects very small heat variation across a sample, using a lock in amplifier. The system identifies and “localizes” i.e., provides the location coordinates of, defects causing localized heating inside the chip.
Another kind of testing done during design verification is called Thermal Laser Stimulation (TLS or SLS for static laser stimulation). A current product available from the subject assignee using this technique is the MERIDIAN™ or TriVision™. The term TLS refers to using a laser (e.g., 1340 nm wavelength) to create local heating on the semiconductor IC to test the effect of heating on the IC's performance. In such a system, the IC is coupled electrically to a tester and is provided with electrical test signals. A laser source is used to cause local heating and the tester is used to study the electrical response of the IC to such heating. That is, the IC's response to an electrical test signal with and without the laser heating can be compared by examining the electrical output of the IC. In conventional TLS, a continuous wave laser is used to induce heat in the device under test. This technique is used to detect metal shorts inside the device.
With the advancement in complex and stacked-die devices, it becomes increasingly difficult to test devices using traditional techniques. Also, a recent stacked die architecture employs a structure called Through-Silicon Via (TSV). Since TSV have high aspect ratio, it is difficult to evenly fill them with conductive material. However, improperly filled TSV may lead to device performance degradation or even malfunction. Accordingly, new and improved techniques and apparatus are needed to assist in testing such devices.